module load_unit(
  input [7:0] op,
  input [63:0] src1,
  input [63:0] src2,
  input [63:0] imm,

  output sign,
  output [63:0] addr,
  output [3:0] bytes,
  output ren,

  output [63:0] res,
  output valid_o

);
  /*verilator no_inline_module*/ 

wire op_ld/*verilator public_flat*/ ,op_lw/*verilator public_flat*/ ,op_lwu/*verilator public_flat*/ ,op_lh/*verilator public_flat*/ ,op_lhu/*verilator public_flat*/ ,op_lb/*verilator public_flat*/ ,op_lbu/*verilator public_flat*/ ,op_lui/*verilator public_flat*/ ;
assign {op_ld,op_lw,op_lwu,op_lh,op_lhu,op_lb,op_lbu,op_lui} = op; 

assign sign = op_lw|op_lh|op_lb;
assign addr = src1 + imm;
assign bytes = {op_ld,op_lw|op_lwu,op_lh|op_lhu,op_lb|op_lbu};

assign ren = op_ld|op_lw|op_lwu|op_lh|op_lhu|op_lb|op_lbu;
assign valid_o = op_lui;
assign res = {64{op_lui}}&imm;
endmodule
